📄️ Architecture Overview
SHDL uses a multi-stage compilation pipeline that transforms high-level hardware descriptions into highly optimized, executable simulations.
📄️ Flattening Pipeline
The flattener transforms Expanded SHDL into Base SHDL through five sequential phases. Each phase must complete before the next begins.
📄️ Base SHDL
Base SHDL is the canonical, minimal representation of an SHDL circuit. It serves as the intermediate representation between the high-level Expanded SHDL and the generated C code.
📄️ Compiler Internals
The SHDL compiler transforms Base SHDL into highly optimized C code. This page explains how the code generation works and the optimization techniques used.
📄️ PySHDL Internals
PySHDL is the Python implementation of the SHDL toolchain. This page documents its internal architecture and module structure.